D-Wave lets BBVA test its next quantum computer in simulation

D-Wave opened a beta of its gate-model quantum simulator on 1 October 2026 to customers including the bank BBVA, FirstQFM, Florida Atlantic University and the Jülich Supercomputing Centre, the company announced. The simulator models up to 21 qubits of the dual-rail design D-Wave is building for its gate-model computers, and runs through its Leap cloud service and Ocean software kit.

D-Wave’s commercial machines today are annealers, which customers such as AT&T use for optimisation problems, and the company describes itself as the only one developing both annealing and gate-model systems. Its gate-model hardware is in development, so beta customers write and test programs on a simulation of the chip, including the errors it is expected to make.

What can beta customers do with the simulator?

Beta customers can program up to 21 simulated qubits, in an ideal mode or a hardware-emulation mode that adds D-Wave’s error model, according to D-Wave’s announcement of 18 June 2026 and its data sheet. D-Wave calls the approach error-aware programming: a program sees when the hardware detects an error and can respond to it as the computation runs.

“What makes our approach different is that error awareness is built into the architecture through dual-rail technology, giving developers access to error-detection data and real-time control capabilities that can help them design more resilient quantum applications,” said Trevor Lanting, D-Wave’s chief development officer, in June.

D-Wave plans development bundles that combine simulator time with access to its future gate-model systems and expert guidance. Its June announcement named Starter and Premium packages with monthly access allocations, priced on request.

How does a dual-rail qubit catch its own errors?

A dual-rail qubit holds one photon across two superconducting microwave cavities, and when that photon is lost the qubit flags the error, which D-Wave said on 5 August 2026 accounts for about 90% of its errors while it idles. A photon in the left cavity reads as 0 and a photon in the right cavity as 1, and the qubit can also hold both at once, D-Wave’s engineers explain in a blog post. The photon is occasionally lost through tiny imperfections in the hardware or interactions with the surroundings, and then neither cavity holds it. The qubit detects that and flags it as an erasure.

A flagged error is easier to fix because its location is known. “In general, a code that corrects up to n bit flips can correct up to 2n erasures,” the blog post says. D-Wave calls this an error hierarchy: the most common errors are also the easiest to correct.

D-Wave’s Nature paper, published on 5 August 2026, showed that the hierarchy largely survives a two-qubit gate between dual-rail qubits. The gate takes about 500 nanoseconds, with erasures of about 0.5% per gate, remaining errors below 0.1% and bit flips practically non-existent, at around one in a million. The gate “is already integrated into our gate-model systems, where it is delivering comparable performance”, D-Wave’s chief scientist Rob Schoelkopf said in the company’s release.

Who is testing it, and what for?

The four beta participants D-Wave named on 1 October 2026 are BBVA, FirstQFM, Florida Atlantic University and the Jülich Supercomputing Centre, each with its own work in mind.

“Error detection creates an opportunity to recover useful information that might otherwise be discarded,” said Ramakrishnan of FirstQFM. “Quantum machine learning models that perform well under ideal conditions may behave very differently when exposed to realistic hardware constraints,” said Arslan Munir, a professor of electrical engineering and computer science at Florida Atlantic.

AT&T, which uses D-Wave’s annealers in its network operations, is also evaluating the forthcoming gate-model systems for quantum security and quantum communications, D-Wave said on 27 July 2026.

D-Wave paid $550 million for Quantum Circuits

D-Wave got its dual-rail technology by buying Quantum Circuits for $550 million, $300 million in D-Wave shares and $250 million in cash, in a deal agreed on 7 January 2026 and completed on 20 January. Rob Schoelkopf, a Yale professor and co-founder of Quantum Circuits whom D-Wave credits as the inventor of the transmon and dual-rail qubit technologies, became D-Wave’s chief scientist, and D-Wave said the deal would add a research and development centre in New Haven, Connecticut.

At the time D-Wave said the first product of its faster gate-model roadmap would be an initial dual-rail system, planned for general availability in 2026.

When does the real hardware arrive?

D-Wave’s gate-model roadmap, set out with its second-quarter results on 6 August 2026, plans a 17-physical-qubit system in 2026 and a 100-logical-qubit machine in 2032. A logical qubit spreads one qubit’s information across many physical qubits so that their errors can be found and corrected.

D-Wave is aiming for an error reduction rate, which it calls Lambda, of 10: the system becomes 10 times more reliable with each increment in error correction, the company says. D-Wave names the first three systems DR17, DR49 and DR181.

D-Wave’s CHIPS Act agreement with the US Department of Commerce, worth up to $100 million and finalised on 8 September 2026, supports a 10,000-qubit gate-model system designed to enable 100 logical qubits, the capability the roadmap schedules for 2032, alongside a 100,000-qubit annealing system. The department takes a minority, non-controlling equity stake in D-Wave as a condition of the money.