IonQ ran real-time error decoding for a simulated quantum computer on one laptop chip, and will put a machine in Nvidia's lab

IonQ said on 22 September 2026 that it had run the error-correction decoder for a 408-logical-qubit quantum computer in real time on one laptop processor, an Apple M4 Max. In the largest of three benchmarks, decoding delays added 0.02% to the run. The quantum computer in the test was a simulation.

The next morning, 23 September, IonQ said a Superion 256 will be the first quantum processor installed at Nvidia’s Accelerated Quantum Research Center in Boston, in 2027. IonQ shares opened 12.5% higher that day and closed up 4.4% at $42.54, according to Nasdaq’s price history.

What does a decoder do?

A decoder is the conventional software that works out which errors a quantum computer has just made, round after round, fast enough to keep the machine running at full speed. Quantum error correction spreads each reliable logical qubit across many fragile physical qubits. The hardware then runs repeated rounds of error checks, called syndrome-extraction cycles, whose results show where errors have probably struck while leaving the stored data intact.

Those results stream to a classical computer, and the decoder turns them into corrections. IonQ’s design keeps the corrections as a running software record called the Pauli frame. When the decoder falls behind, work piles up, and the IonQ paper warns of “a decoding backlog that can induce an exponential slowdown of the quantum computation”.

IonQ splits the work between two decoders

IonQ runs two sliding-window decoders on every code block: one keeps the error record, and the other hurries out measurement results. The error decoder runs all the time. It reads five rounds at once, commits to the first three and produces the corrections used for the whole computation. The outcome decoder switches on only during a logical measurement, reads two rounds and commits one, so it answers sooner.

Speed counts there because the next step of a program often depends on a measurement’s outcome. If the decision is late, the authors write, “the measurement must continue for an additional cycle, delaying all subsequent operations that depend on its outcome”. Min Ye, Andrii Maksymov and Nicolas Delfosse, all of IonQ, posted the paper to arXiv on 25 August 2026 and revised it on 3 September.

The design leans on IonQ’s Walking Cat architecture, in which logical operations add extra measurements to an otherwise unchanged stream of error checks. The decoder therefore keeps one fixed decoding graph and changes only its error probabilities as measurements come and go, which is light enough to run on the same CPU.

The qubits were simulated and the timing was real

IonQ simulated the quantum machine and timed the decoding for real on a 2024 MacBook Pro’s Apple M4 Max chip, using 12 of its 16 cores. Eight cores ran the error decoder and four the outcome decoder. A circuit-level simulation produced the error-check data a trapped-ion computer would generate. The largest benchmark models 68 memory blocks and 20 magic-state factories, which prepare the resource each T gate consumes, built from 11,680 physical qubits.

The paper assumes one error-check round every 1 ms or 5 ms, which it calls representative long-term and near-term trapped-ion timescales. Two-qubit gate error rates run from one to five in 10,000. Stretch is the share of extra rounds the machine runs while it waits for the decoder.

IonQ’s headline 0.02% comes from the largest circuit at the 5 ms round, which gives each core five times as long per round to handle four times as many blocks. At the 1 ms round the two 102-qubit circuits stretched by 0.18% and 0.24%, and at the highest error rate tested the stretch reached 11.53%. The 31.5 million “operations” in IonQ’s release are the paper’s count of error-check rounds, summed across all 88 blocks.

Why can a laptop chip keep up?

A laptop chip keeps up because trapped-ion error-check rounds last milliseconds, and because IonQ’s architecture keeps the decoding problem simple. Superconducting quantum computers work to microsecond deadlines, the IonQ paper notes, so their decoders have moved onto specialised hardware: FPGAs, TPUs, GPUs and custom ASICs. Nvidia released its own GPU-based Ising decoder on 13 July 2026.

IonQ calls its result the industry’s first end-to-end real-time decoder. The paper’s survey of earlier streaming decoding lists a 15-logical-qubit magic-state factory, and random measurements across 100 small surface codes on a network of FPGAs. Delfosse, IonQ’s quantum research lead, said in the release that “the fact that our decoder runs on a single CPU provides a practical path to commercial-scale fault-tolerant quantum computing”.

Nvidia’s Boston lab will host a Superion 256

An IonQ Superion 256 will be the first quantum processor at the NVIDIA Accelerated Quantum Research Center (NVAQC) in Boston, with installation scheduled for 2027. IonQ announced it on 23 September 2026. The machine will link to an Nvidia GB200 NVL72 rack-scale system through NVQLink, Nvidia’s interconnect between quantum processors and GPUs, with work orchestrated on the open CUDA-Q platform.

Nvidia announced the centre on 18 March 2025, naming Quantinuum, Quantum Machines and QuEra among the companies that would use it. Its NVAQC page says error-correction tasks such as decoding call for AI and GPU-acceleration techniques, which the centre will develop. Timothy Costa, Nvidia’s vice president and general manager for quantum, said in IonQ’s release: “Every supercomputer will become a quantum supercomputer.” The joint programme focuses on hybrid software and large-scale system prototyping, and is expected to target portfolio optimisation and risk modelling, materials science and chemistry for drug discovery.

Superion 256 is IonQ’s sixth-generation platform, launched on 8 September with first customer deliveries expected in 2027; our launch report covers it. Chief executive Niccolo de Masi said IonQ’s “roadmap to 10,000 qubits and full fault tolerance is accelerating through vertical integration of our SkyWater CMOS foundry”.

How did IonQ shares react?

IonQ shares opened at $45.84 on 23 September 2026, 12.5% above the previous close, touched $46.05, then gave back most of the gain to close at $42.54, up 4.4%. Volume reached 72.6 million shares, about four times the 17.9 million of the day before, according to Nasdaq’s price history. IonQ published the decoder release at 16:00 New York time on 22 September, as trading closed, and the Nvidia release at 08:00 the next morning, so 23 September was the first session to trade on both. Yahoo Finance reported a 5% rally in morning trade, crediting both announcements.

By the close on 25 September the shares stood at $45.48, 11.6% above their level before the decoder news.

Bigger machines just add CPU cores

The paper’s provisioning rule is that decoding compute grows mainly with the number of code blocks each core has to handle. A larger machine therefore needs more conventional CPU cores or more CPUs, which the authors call “a natural path to larger machines”. IonQ ties the result to its roadmap beyond 256 physical qubits, toward platforms controlling thousands. It expects first Superion 256 deliveries in 2027, the same year its machine is due in Nvidia’s Boston lab.